In computing, interleaved memory is a design which compensates for the relatively gradual velocity of dynamic random-access memory (DRAM) or core memory, by spreading Memory Wave Method addresses evenly across memory banks. That means, contiguous memory reads and writes use each memory bank in turn, leading to higher memory throughput on account of diminished ready for memory banks to become prepared for the operations. It is totally different from multi-channel memory architectures, primarily as interleaved memory does not add extra channels between the main memory and the memory controller. Nonetheless, channel interleaving can also be potential, for example in freescale i.MX6 processors, which allow interleaving to be achieved between two channels. With interleaved memory, memory addresses are allotted to each memory bank in flip. For instance, in an interleaved system with two memory banks (assuming phrase-addressable memory), if logical handle 32 belongs to financial institution 0, then logical address 33 would belong to financial institution 1, logical address 34 would belong to bank 0, and so on. An interleaved memory is said to be n-way interleaved when there are n banks and memory location i resides in bank i mod n.

Interleaved memory ends in contiguous reads (that are widespread both in multimedia and execution of packages) and contiguous writes (that are used frequently when filling storage or communication buffers) truly using every memory financial institution in flip, as an alternative of using the identical one repeatedly. This ends in considerably increased memory throughput as every financial institution has a minimal ready time between reads and writes. Major memory (random-access memory, RAM) is usually composed of a collection of DRAM memory chips, the place a number of chips might be grouped together to kind a memory financial institution. It's then attainable, with a memory controller that supports interleaving, to lay out these memory banks so that the memory banks will be interleaved. Knowledge in DRAM is saved in models of pages. Each DRAM financial institution has a row buffer that serves as a cache for accessing any page in the bank. Before a page in the DRAM financial institution is learn, it's first loaded into the row-buffer.

If the page is immediately learn from the row-buffer (or a row-buffer hit), it has the shortest memory access latency in one memory cycle. If it's a row buffer miss, which can also be known as a row-buffer conflict, it is slower as a result of the brand new web page has to be loaded into the row-buffer before it is read. Row-buffer misses happen as entry requests on completely different memory pages in the same bank are serviced. A row-buffer conflict incurs a considerable delay for a memory entry. In contrast, memory accesses to different banks can proceed in parallel with a high throughput. The problem of row-buffer conflicts has been well studied with an effective resolution. The scale of a row-buffer is normally the scale of a memory web page managed by the operating system. Row-buffer conflicts or misses come from a sequence of accesses to difference pages in the same memory financial institution. The permutation-based interleaved memory technique solved the problem with a trivial microarchitecture cost.

Solar Microsystems adopted this the permutation interleaving technique quickly of their products. This patent-free method can be discovered in lots of industrial microprocessors, reminiscent of AMD, Intel and NVIDIA, for embedded methods, laptops, desktops, Memory Wave and enterprise servers. In traditional (flat) layouts, memory banks could be allocated a contiguous block of memory addresses, which is quite simple for the memory controller and gives equal efficiency in utterly random access situations, when compared to efficiency ranges achieved by means of interleaving. Nonetheless, in actuality memory reads are hardly ever random as a result of locality of reference, and optimizing for Memory Wave close collectively access provides much better performance in interleaved layouts. The best way memory is addressed has no effect on the access time for memory locations that are already cached, having an influence only on memory locations which have to be retrieved from DRAM. Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang (2000). A Permutation-primarily based Web page Interleaving Scheme to cut back Row-buffer Conflicts and Exploit Knowledge Locality. Department of Pc Science and Engineering, School of Engineering, Ohio State College. Mark Smotherman (July 2010). "IBM Stretch (7030) - Aggressive Uniprocessor Parallelism".